Synchronous memory circuits contain a multiplicity of addressable memory cells for storing data. Following the manufacturing process, the memory circuits produced are tested for operability by a test arrangement before they are delivered.
FIG. 1 shows a teat arrangement based on the prior art. The circuit to be tested DUT (DUT: Device Under Test) is clocked with a clock signal CLK via a clock signal line by the external test unit and receives test control signals via a control bus for the purpose of testing a synchronous memory circuit. The test unit uses a data bus to write test data patterns to the memory cells addressed via the address bus and to read them out of the memory cells again. The test unit compares the applied test data with the data which are read out and, on the basis of the data discrepancies established, establishes which memory cells within the synchronous memory are faulty. These memory cells are generally replaced with redundant memory cells by means of readdressing. If the number of faulty memory cells within the synchronous memory circuit is too high, the memory to be rested DUT is disposed of as being irreparable. Testing the synchronous memory DUT involves data being written to the memory and then being read out again.
FIG. 2 shows signal diagrams to illustrate the writing of data to the synchronous memory chip. The memory chip is clocked with a clock signal CLK by the test unit and receives via the control bus a command to write data to the addressed memory cell, After a latency LWR, the data to be written Dln are applied to the data connection of the synchronous memory chip. For critical testing of the memory chip DUT, the latencies can be adjusted by the external lest unit.
FIG. 3 shows flow diagrams to illustrate the read operation for data from the synchronous memory chip. The memory cells contained in the memory chip are arranged in the form of a matrix and are addressed by means of a row address strobe signal (RAS) and a column address strobe signal (CAS). The RAS control signal, which the test unit applies to the synchronous memory chip via the control bus, indicates that the address present on the address bus is a row address, while a CAS control signal indicates that the address present on the address bus is a column address. Successive application of a column address and a row address allows a specific memory cell to be addressed. The use of an RAS control signal and a CAS control signal allows the width of the address bus to be kept down.
As FIG. 3 reveals, the test unit applies a read command to the synchronous memory chip via the control bus, and the data on the data connections DQ are read out after a CAS latency. In this case, FIG. 3 shows various CAS latencies which can be adjusted by the external test unit.
The synchronous memory chip DUT operates at a particular operating clock frequency CLK. In modern memory chips, the operating clock frequencies are becoming higher and higher and are already in the region of a few hundred megahertz. Conventional test units operate at operating clock frequencies of, by way of example, 100 megahertz and are not able to test such high-frequency memory chips reliably.